Warning: WP Redis: Connection refused in /www/wwwroot/cmooc.com/wp-content/plugins/powered-cache/includes/dropins/redis-object-cache.php on line 1433

# 超大规模集成电路计算机辅助设计 1：逻辑

## VLSI CAD Part I: Logic

2650 次查看

Coursera
• 完成时间大约为 23 个小时
• 中级
• 英语

Logic Gate

Digital Design

Boolean Algebra

### 课程概况

A modern VLSI chip has a zillion parts — logic, control, memory, interconnect, etc. How do we design these complex chips? Answer: CAD software tools. Learn how to build thesA modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this first part of the course is on key Boolean logic representations that make it possible to synthesize, and to verify, the gate-level logic in these designs. This is the first step of the design chain, as we move from logic to layout. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: Computational Boolean algebra, logic verification, and logic synthesis (2-level and multi-level).

### 课程大纲

Orientation
In this module you will become familiar with the course and our learning environment. The orientation will also help you obtain the technical
skills required for the course.
1 个视频 （总计 25 分钟）, 2 个阅读材料, 5 个测验

Computational Boolean Algebra
In this module, we will introduce advanced Boolean algebra math concepts that make it possible to take a "computational" approach to
Boolean algebra.
6 个视频 （总计 91 分钟）, 2 个阅读材料

Boolean Representation via BDDs and SAT
Week 2 introduces two powerful and important representation techniques that allow us to do SERIOUS computational Boolean algebra, on
industrial-scale designs.
7 个视频 （总计 135 分钟）, 2 个阅读材料, 2 个测验

2-Level Logic Synthesis, and Multi-Level Logic Synthesis via the Algebraic Model
In Week 3, we will move from "representing" things to "synthesizing" things. In this case, synthesis means "optimization", or maybe the word
"minimization" is more familiar from hand work with Kmaps or Boolean algebra.
8 个视频 （总计 119 分钟）, 2 个阅读材料, 1 个测验

Multilevel Factor Extract and Don't Cares
You now know that to factor a multi-level network to reduce its complexity, you must look at the kernels and co-kernels. You know how to "get" these for any node. But -- what do you do with a big network to actually FIND the right common divisors? This is called EXTRACTION. We then look at a new opportunity to optimize multi-level logic: Don't Cares. In simple designs, we usually regard Don't Cares as "impossible inputs" -- things that just do not happen, so we can choose the value the hardware creates to minimize the logic.
8 个视频 （总计 123 分钟）, 2 个阅读材料, 3 个测验

Final Exam
There is no new content this week. Instead, you should focus on finishing the last problem set and completing the Final Exam.

### 常见问题

Apple 广告
##### 声明：MOOC中国十分重视知识产权问题，我们发布之课程均源自下列机构，版权均归其所有，本站仅作报道收录并尊重其著作权益。感谢他们对MOOC事业做出的贡献！
• Coursera
• edX
• OpenLearning
• FutureLearn
• iversity
• Udacity
• NovoEd
• Canvas
• Open2Study
• ewant
• FUN
• IOC-Athlete-MOOC
• World-Science-U
• CourseSites
• opencourseworld
• ShareCourse
• gacco